Deep dives into AI agents for EDA, SystemC internals, ARM architecture, and the hardware-software boundary where real engineering happens — written by someone building this stuff at Synopsys R&D.
// Latest Posts
From Cortex-A to Cortex-M — how ARM diversified into three major categories and revolutionized mobile and embedded computing.
read →How vptr and vtbl work under the hood — from simple object models to the complete C++ object layout.
read →Pin threads to cores for deterministic performance. A practical guide to CPU affinity in multi-core systems.
read →Efficient logging strategies for resource-constrained environments where every byte and cycle counts.
read →Memory layout, alignment, and when to choose one over the other in embedded firmware development.
read →Why volatile matters for hardware registers, ISRs, and multi-threaded access — and what the compiler really does without it.
read →// Explore
Cortex-A, R, M series & micro-architecture internals
Object models, pointers, volatile, storage classes
Real-time logging, firmware, IoT device programming
Threads, CPU affinity, RTOS task management
sc_module, TLM 2.0 sockets, virtual platforms & ESL design
LLM-powered agents for hardware verification, spec-to-test generation, and agentic EDA workflows.
// What I Offer
Core learning for ports, signals, clocks, and data types. Build correct SystemC models step-by-step after signup.
TLM, advanced channel concepts, SCV-style verification, platform composition, and production-grade workflow. Paid access placeholder.
// About
I write about the things that live beneath the abstractions — processor pipelines, memory hierarchies, compiler behaviors, and the hardware-software boundary where real engineering happens.
Right now I'm building LLM-powered agents at Synopsys R&D that automate hardware verification — and writing about what that actually looks like from the inside.
ErrBits is a place to debug assumptions and understand how machines truly work, one bit at a time.