What you'll learn
- SystemC language fundamentals — modules, processes, signals, events
- TLM 2.0 transport interface — sockets, generic payload, timing
- Modeling platform IPs — timers, clocks, resets, interrupt controllers
- Register modeling patterns — status, control, interrupt registers
- Virtual platform integration — bus fabric, address maps, clock trees
- Debug and verification techniques for TLM models
#include <systemc.h>
#include <tlm.h>
class Timer : public sc_module,
public tlm::tlm_fw_transport_if<> {
public:
tlm::tlm_target_socket<> socket;
sc_out<bool> irq;
SC_CTOR(Timer) : socket("socket") {
socket.bind(*this);
SC_THREAD(tick_thread);
}
void b_transport(tlm::tlm_generic_payload&, sc_time&);
void tick_thread();
};
SystemC Foundations
What is SystemC and Why It Exists
The motivation behind SystemC, how it differs from RTL simulation, and where it fits in the hardware design flow.
Anatomy of sc_module
Modules, ports, processes (SC_METHOD, SC_THREAD), sensitivity lists, and the simulation kernel event loop.
Signals, Events, and Time
sc_signal, sc_event, sc_time, wait() semantics, and how simulation time advances in SystemC.
TLM 2.0 Core Concepts
TLM Generic Payload & Transport Interface
Understanding tlm_generic_payload, blocking vs non-blocking transport, and the initiator-target communication pattern.
Initiator & Target Sockets
How TLM sockets work, binding rules, multi-passthrough sockets, and building your first memory target.
Timing Annotation & Quantum Keeper
Loosely-timed vs approximately-timed modeling, temporal decoupling, and the quantum keeper mechanism.
IP & Peripheral Modeling
Modeling a Timer IP
Build a timer with configurable prescaler, auto-reload, capture/compare channels, and interrupt generation.
Clock & Reset Controllers
Modeling clock generation, PLL configuration, clock gating, reset sequencing, and power domain management.
Interrupt Controllers & Aggregators
Modeling interrupt routing, priority encoding, masking, pending/clear registers, and cascaded interrupt lines.
Watchdog Timer
Building a watchdog with window mode, early warning interrupt, and system reset generation on timeout.
Register Modeling Patterns
Status, control, and data registers. Read/write behaviors, write-1-to-clear, reserved bits, and access restrictions.
Virtual Platform Integration
Bus Fabric & Address Decode
Connecting IPs to a bus, address map configuration, bus bridges, and multi-layer interconnects.
Clock Trees & Reset Domains
Modeling system-level clock distribution, reset propagation, and power-on sequences across the platform.
Debug & Verification
Simulation Log Analysis
Reading simulation output, tracing TLM transactions, identifying read/write failures, and common error patterns.
Common Pitfalls & Best Practices
Deadlocks, delta-cycle issues, incorrect sensitivity, payload reuse bugs, and how to avoid them.